Rockchip "PCIe Link Fail" / "Phy link never came up": NVMe Not Detected
PCIe Link Fail
The PCIe controller probed but link training with the device failed. Vendor kernels print "PCIe Link Fail"; mainline DesignWare PCIe prints "Phy link never came up".
Applies to: RK3588 RK3588S RK3576 RK3568 RK3566 RK3528 RK3399
Symptoms
- dmesg shows "PCIe Link Fail" (vendor kernel) or "Phy link never came up" (mainline)
- lspci is empty and there is no /dev/nvme0n1
Common causes
- M.2 slot unpowered: wrong vpcie3v3 regulator or enable GPIO
- Wrong PERST# reset GPIO or polarity
- PHY node disabled, or combo PHY left in SATA/USB mode
- Lane / bifurcation config does not match the board
- Signal integrity problems at Gen3
- SSD is M.2 SATA, not NVMe
How to fix it
- Collect the evidence
dmesg | grep -iE 'pcie|phy|nvme' lspci -nn - Check power and reset in the DTS
&pcie3x4 { reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PERST#: match schematic */ vpcie3v3-supply = <&vcc3v3_pcie30>; status = "okay"; }; - Enable the PHY and match lane mode
Enable pcie30phy (or the combo PHY for PCIe 2.1 x1 ports) and make num-lanes/bifurcation match the routed lanes.
- Force a lower link speed to test signal integrity
&pcie3x4 { max-link-speed = <2>; };
Go deeper
FAQ
What does "PCIe Link Fail" mean?
The PCIe controller probed but link training with the device failed. Vendor kernels print "PCIe Link Fail"; mainline DesignWare PCIe prints "Phy link never came up".
What causes "PCIe Link Fail"?
M.2 slot unpowered: wrong vpcie3v3 regulator or enable GPIO; Wrong PERST# reset GPIO or polarity; PHY node disabled, or combo PHY left in SATA/USB mode; Lane / bifurcation config does not match the board; Signal integrity problems at Gen3; SSD is M.2 SATA, not NVMe.
How do I fix "PCIe Link Fail"?
1. Collect the evidence 2. Check power and reset in the DTS 3. Enable the PHY and match lane mode: Enable pcie30phy (or the combo PHY for PCIe 2.1 x1 ports) and make num-lanes/bifurcation match the routed lanes. 4. Force a lower link speed to test signal integrity
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