Rockchip Ethernet
GMAC, RGMII delays, PHY bring-up and 2.5 GbE over PCIe on Rockchip.
Rockchip SoCs integrate Synopsys GMACs (stmmac / dwmac-rk driver) connected over RGMII or RMII to an external PHY. Boards with 2.5 GbE usually add a PCIe NIC such as the RTL8125. RGMII timing (tx_delay/rx_delay or rgmii-id modes), PHY reset and the clock source cause most link problems.
Key points
- phy-mode ("rgmii", "rgmii-id", "rgmii-rxid"…) and the MAC delay values must agree. Do not double-add delays.
- Check the PHY ID over MDIO first; if the PHY is not detected, look at reset GPIO timing and power.
- clock_in_out selects whether the 125 MHz / 50 MHz reference comes from the SoC or the PHY.