Rockchip MIPI
MIPI CSI-2 cameras and MIPI DSI displays: lanes, PHYs and device-tree graphs.
MIPI on Rockchip covers camera input (CSI-2 over D-PHY, plus C-PHY on RK3588) and display output (DSI). Both are described as device-tree graphs of endpoints linking the sensor or panel, the PHY, and the ISP or VOP. Lane count, link frequency and data-lanes mapping must match on every endpoint.
Key points
- Sensor → csi2_dphy → mipi_csi2 → rkcif / rkisp: each hop needs matching endpoints and lane counts.
- DSI panels need the correct init sequence, timings and reset/backlight GPIOs.
- Use media-ctl -p to inspect the camera pipeline the kernel actually built.